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인증된 전문가에게 직접 연결
인증된 전문가에게 직접 연결
Manufacture: Terasic
Model: Altera DSP
1. Featured device:
Stratix V GS FPGA: 5SGSMD5K2F40C2N
2. Configuration, status, and setup elements
JTAG
On-board USB-BlasterTM II cable
Fast passive parallel (FPP) configuration via MAX® V device and flash memory
One reset config push button
One CPU reset push button
Two configuration push buttons
3. Clocks
50-MHz and 125-MHz programmable oscillators
SMA input (LVPECL)
4. General user input and output
10/100/1000Mbps Ethernet PHY (SGMII) with RJ-45 (copper) connector
16x2 character LCD
One 8-position dual in-line package (DIP) switch
Sixteen user LEDs
Three user push buttons
5. Memory devices
DDR3 SDRAM (1,152 MB, x72-bit wide)
QDR II+ SRAM (4.5 MB, 2-Mb x18-bit wide)
Footprint compatible to QDR II 4-Mb x18-bit wide
RLDRAM II (72-Mbyte CIO RLDRAM II with an 18-bit data bus)
6. Component and interfaces
PCIe x8 edge connector
Two HSMC connectors
SMB for serial digital interface (SDI) input and output
QSFP optical cage
10/100/1000Mbps Ethernet PHY (SGMII) with RJ-45 (copper) connector
7. Power
Laptop DC input
PCIe edge connector
Nios® II processor web server and remote system update
The DSP Development Kit, Stratix® V Edition provides a complete design environment that includes all the hardware and software you need to begin developing DSP-intensive FPGA designs immediately. The development kit is RoHS compliant. You can use this development kit to do the following:
