1. High-Speed Signal Validation in AI Systems
Modern AI systems must transfer large volumes of data between processors, GPUs, memory, and expansion components. Interfaces such as Peripheral Component Interconnect Express (PCIe), Compute Express Link (CXL), and chip-to-chip interconnects increasingly require high bandwidth and low latency. As data rates increase, even small deviations in amplitude, timing, or impedance can compromise transmission reliability.
PCIe 6.0 uses four-level pulse amplitude modulation (PAM4) to achieve 64 GT/s per lane, while PCIe 7.0 doubles this rate to 128 GT/s. PAM4 uses four voltage levels instead of the two levels employed by non-return-to-zero (NRZ) signaling, allowing two bits to be transmitted per symbol. However, the smaller voltage separation between levels makes the signal more susceptible to noise, crosstalk, channel loss, and jitter, all of which can affect data discrimination.
Engineers need to inspect transmitter waveforms, evaluate signal quality at the receiver, and determine the available channel margin under different operating conditions. High-speed oscilloscopes combined with signal analysis software can measure eye diagrams, jitter, rise time, fall time, and other parameters associated with signal integrity.
For PAM4 interfaces, evaluating all three eye openings and the linearity between signal levels helps reveal deviations that conventional amplitude measurements may not fully capture. Interface compliance testing is also necessary to verify that the design meets the applicable technical requirements before system integration.
2. Electrical Characterization of Next-Generation Chips
A chip's electrical characteristics are reflected not only in its data-processing capabilities but also in power supply stability, signal response, and behavior during operating-state transitions. AI processors and accelerators can experience rapid changes in power consumption as computational workloads fluctuate. If the power delivery network cannot respond quickly enough, voltage droop or transient noise may occur at the power supply pins, potentially disrupting high-speed digital circuits.
Measuring power supply noise and transient voltage droop helps engineers establish the relationship between supply quality and signal errors. For detailed analysis, engineers can use oscilloscopes with suitable probes to observe voltage ripple, power supply noise, and variations during load transitions. Measurements taken close to the load provide a more accurate representation of the electrical conditions experienced by the chip.
For high-speed interfaces, measurements should consider transmitted signals, power supply quality, and the effects of the interconnect simultaneously. Channel loss, reflections caused by impedance discontinuities, and crosstalk can distort waveforms at the receiver. Meanwhile, power supply noise can shift signal transition timing or reduce the available signal amplitude margin.
Measurements should be performed across multiple load levels and temperature conditions. Comparing data under idle, moderate-load, and heavy-load conditions helps identify deviations that occur only when the system approaches its design limits. These comparisons also help determine whether a problem originates in the chip, power delivery network, circuit board, or interconnect between components.
3. Measuring and Optimizing Energy Efficiency in AI Infrastructure
Power consumption in AI infrastructure depends on processors, memory, data transmission systems, and supporting equipment. Monitoring only total server power makes it difficult to identify which components contribute to energy losses or reduce computational performance per watt.
Simultaneously measuring voltage, current, and power over time helps identify periods of unusually high energy consumption. By correlating electrical measurements with computational workloads, data transfer rates, and temperature, engineers can determine whether increased power consumption delivers a corresponding improvement in processing performance.
At the chip level, engineers need to consider dynamic power, static power, and losses associated with switching activity. Increasing clock frequency or supply voltage can improve performance but also raises power consumption. Conversely, reducing the supply voltage too aggressively may decrease operating margins and increase the risk of errors under certain conditions.
For high-speed interconnects, energy optimization does not mean reducing power consumption at any cost. The design must maintain signal quality and keep the bit error rate within acceptable limits. Adjustments to transmitters, receivers, equalization circuits, and power management modes should be guided by measurement data to avoid sacrificing reliability for lower power consumption.
One useful metric for evaluating a system is the energy consumed per unit of completed work. This metric should be measured under defined test conditions, computational workloads, and service quality requirements. It enables engineers to compare hardware configurations and operating modes based on actual performance rather than nominal power consumption alone.
4. Establishing a Validation Workflow Before System Integration
The validation process should begin with the most critical interfaces, particularly those connecting processors, AI accelerators, and memory. Before selecting test equipment, engineers need to identify the interface standard, data rate, signal quality requirements, and operating conditions.
During physical-layer testing, high-speed oscilloscopes capture waveforms and evaluate parameters such as eye diagrams, jitter, noise, and signal quality at the transmitter or receiver. For PAM4 designs, engineers must apply measurement methods and evaluation limits appropriate to the specific standard revision being implemented.
Next, power supply testing identifies voltage droop, noise, and transient response during load changes. Power measurements are then performed under representative operating modes to evaluate energy consumption. If anomalies are detected, engineers can correlate waveform, power supply, and power consumption data to isolate the underlying cause.
In the final stage, compliance testing and interoperability assessments help reduce integration risks. For PCIe, CXL, and other high-speed interfaces, meeting the requirements at the individual component level does not guarantee stable system-wide operation. The design must be evaluated in its actual interconnect configuration, including circuit boards, connectors, transmission lines, and intermediate components.
Measurement data should be stored alongside design revisions, test conditions, and hardware configurations. This approach allows engineers to compare results across design iterations, determine the impact of individual changes, and shorten debugging time.
5. Test Equipment for Chip Development and AI Infrastructure
For high-speed interface designs, the Tektronix DPO77002SX oscilloscope supports PAM4 signal analysis, jitter measurements, and signal integrity testing with bandwidths of up to 70 GHz. When equipped with the appropriate software, the instrument can support validation of next-generation PCIe interfaces, helping engineers assess signal quality before hardware integration.
At the circuit level, the MSO68B and MSO64B, part of the 6 Series B MSO family, support multichannel signal analysis, power supply noise measurements, and signal integrity investigations. For measurements focusing on power management ICs, power distribution networks, and power sequencing, the MSO58B, part of the 5 Series B MSO family, is a suitable option.
Instrument selection should be based on signal speed, measurement bandwidth, probe type, and the required analysis software. Combining interconnect validation with power supply analysis helps engineers better understand the relationship between signal quality, chip stability, and energy consumption in AI systems.
Tektronix Semiconductor 2026 Event Information
To provide updates on emerging semiconductor material testing technologies and demonstrate comprehensive testing solutions spanning R&D to Failure Analysis, EMIN Vietnam, in collaboration with Tektronix, is organizing a specialized technical seminar.
Event: Tektronix Semiconductor 2026
Date and Time: Wednesday, November 11, 2026, from 9:00 AM to 2:00 PM
Venue: National Innovation Center (NIC), Alley 7, Ton That Thuyet Street, Cau Giay District, Hanoi, Vietnam
Key Topics: Semiconductor technologies (SiC/GaN), reliability testing and evaluation solutions, and in-depth failure analysis.
For more information and to register for the seminar, click here.
